A conventional field effect semiconductor device, such as a silicon MOSFET, permits large-scale integration of elements and has various functions. Furthermore, improvements in operating speed are being made and the gate length is being progressively shortened and the thickness of the gate oxide film is becoming progressively thinner.
However, there is a problem in that as the gate length is made progressively shorter, the leakage current becomes more liable to flow into the channel when the drain current is off. This is because the standby power becomes notable when the scale of integration is increased, and therefore is undesirable from the viewpoint of power consumption. Consequently, a device structure which suppresses power consumption has been sought. For example, a tunnel FET using a tunneling effect has been proposed, instead of a conventional FET which electrons travel in the channel by diffusion drift (see, for example, Appl. Phys. Lett. Vol. 67, 494 (1995)), and therefore this composition is explained with reference to FIGS. 7 to 9B.
FIG. 7 is a schematic cross-sectional diagram of a conventional tunnel FET, in which a p++-type source region 64 and an n++-type drain region 65 doped with a high concentration of impurities that enables degeneration of the carrier are provided in a p-type silicon substrate 61, and a gate electrode 63 is provided on a gate insulating film 62 between these regions. The reference numerals 66 and 67 in FIG. 7 indicate a source electrode and a drain electrode.
FIGS. 8A to 8C are principal band diagrams of a conventional tunnel FET, where FIG. 8A is a band diagram of an unbiased state, in which the carrier degenerates, and therefore the Fermi level Efp is to the lower side of the valence band Evp in the p++-type source region 64. On the other hand, the Fermi level Efn is to the upper side of the conduction band Ecn in the n++-type drain region 65.
FIG. 8B is a band diagram of a state where the gate potential Vg is applied to the gate electrode 63, and in this state, the drain potential Vd is not applied to the drain electrode 67 and therefore the carrier does not flow.
FIG. 8C is a band diagram of a state where the gate potential Vg is applied to the gate electrode 63 and a drain potential Vd is applied to the drain electrode 67. In this state, the electrons injected from the p++-type source region 64 reach the n++-type drain region 65 by a band-to-band tunnel which tunnels through a depletion layer formed at the interface between the p-type silicon substrate 61 and the n++-type drain region 65.
FIGS. 9A and 9B are illustrative diagrams of the characteristics of a conventional tunnel FET, wherein FIG. 9A is a characteristics graph of a conventional two-terminal type device, and FIG. 9B is a characteristics graph of a normal FET using a diffusion current and a tunnel FET. Since the tunnel current rises suddenly in a tunnel FET, then it is possible to reduce the voltage swing between switching on and off of the drain current, and moreover, since the current is reduced suddenly when switched off, then the sub-threshold characteristics (sub-threshold slope) are improved compared to the two-terminal type device characteristics and the normal FET characteristics.
Furthermore, it has also been proposed to introduce a tunnel injection in a GaAs-type HEMT (see, for example, Japanese Patent Application Publication No. H08-186271), and therefore this configuration is described with reference to FIG. 10. FIG. 10 is a schematic cross-sectional diagram of a conventional GaAs tunnel HEMT. An i-type GaAs electron travelling layer 73 is formed via an i-type AlGaAs insulating layer 72 on top of a semi-insulating GaAs substrate 71. An n-type AlGaAs electron supplying layer 74 and an i-type AlGaAs insulating layer 75, and a gate electrode 76 are provided thereon. An n+-type GaAs source region 77 and a p+-type GaAs drain region 78 are provided on either edge of the gate electrode 76. The reference numerals 79 and 80 in FIG. 10 indicate the source electrode and the drain electrode. In this case also, the sub-threshold characteristics are improved in comparison with the characteristics of a two-terminal type device.
On the other hand, there has been an increase in attempts to use compound semiconductors that have higher electron mobility than silicon, in the channels, as a method for raising the speed of MOSFETs instead of shortening the gate length. GaAs is a typical example of a compound semiconductor, but a GaAs MOSFET has not been achieved due to the high number of defect levels in the oxidation film. Therefore, a GaAs HEMT which does not use a gate oxide film (n-type AlGaAs/i-type GaAs hetero-selective doping structure) has been invented. Furthermore, an InP HEMT (n-type InAlAs/i-type InGaAs structure) is also used from the viewpoint of obtaining high speed characteristics.
The source resistance needs to be reduced in order to raise the speed of the InP HEMT, but since a resistance occurs due to the hetero-junction which is characteristic of the HEMT, there still remain problems with improvement, and therefore this situation is described here with reference to FIGS. 11 and 12B. FIG. 11 is a schematic cross-sectional diagram of a conventional InP HEMT. An i-type InAlAs buffer layer 82, an i-type InGaAs channel layer 83, an i-type InAlAs spacer layer 84, a planar doping layer 85, an i-type InAlAs Schottky barrier layer 86 and an n-type InGaAs layer are layered successively on top of the semi-insulating InP substrate 81. A two-dimensional electron gas layer 87 is formed at the interface between the i-type InGaAs channel layer 83 and the i-type InAlAs spacer layer 84. Thereupon, the n-type InGaAs layer is broken up to create n-type InGaAs cap layers 88 and 89, a gate electrode 90 is formed therebetween and a source electrode 91 and a drain electrode 92 are formed on top of the n-type InGaAs cap layers 88 and 89.
FIGS. 12A and 12B are band diagrams of a conventional InP-type HEMT, wherein FIG. 12A is a band diagram along the single-dotted line linking A-A′ in FIG. 11, and FIG. 12B is a band diagram along the single-dotted line linking B-B′ in FIG. 11. As illustrated in FIG. 12A, directly below the gate electrode 90, a drain current flows due to the two-dimensional electron gas layer 87 which is formed at the interface between the i-type InGaAs channel layer 83 and the i-type InAlAs spacer layer 84.
On the other hand, on the source electrode side, as illustrated in FIG. 12B, the i-type InAlAs Schottky barrier layer 86 and the i-type InAlAs space layer 84 form a potential barrier to the electrons, and therefore the source resistance becomes greater.
Furthermore, in recent years, it has been reported that a stable oxide film can be formed on InGaAs (see, for example, Appl. Phys. Lett. Vol. 91, 232107 (2007)), and attention has been drawn to InGaAs channel MOSFETs, rather than HEMT structures.